As is known, the integration of high voltage devices requires the creation of insulating structures having geometrical characteristics such as to prevent setting-up during operation of the circuit of electric fields of high intensity such as may cause an early breakdown of the insulating structures themselves. In particular, critical situations may occur at sharp edges, for example right angles, where, on account of the reduced radius of curvature, the concentration of charge is greater, and consequently the intensity of the local electric field is greater.
In this connection, reference is made to FIG. 1, in which a wafer 1, shown for convenience only in part, comprises a substrate 2, a thin insulating layer 3 on top of the substrate, an insulating structure 4 formed by a field oxide layer, and a conductive region 5, for example of polycrystalline silicon. The insulating structure 4 is delimited by a wall 6 having a nearly vertical inclination, thereby forming with the substrate 2 a right angle .alpha. where, during operation of the device, the intensity of the local electric field is much higher than in the surrounding areas. In a high voltage device, this local peak of electric field may be sufficient to cause early breakdown of the insulating structure 4 also in the case where the average value of the electric field is lower than the values held to be critical.
To solve this problem, high voltage circuits have insulating structures with smaller angles. For example, FIG. 2 shows an insulating structure 7, the physical and geometrical characteristics (in particular, the thickness) of which guarantee the required breakdown value. In particular, the insulating structure 7 has a wall 8 forming an angle .beta. lower than 90.degree. (for example, between 30.degree. and 60.degree.) with respect to the substrate. As a result, given the same operating conditions, the charge density at the angle .beta. is lower than that at the angle .alpha. of FIG. 1, and the intensity of the local electric field is lower. In this solution, however, a transition region 7a exists between the insulating structure 7 and the oxide layer 3. As is obvious, the longer the transition region 7a,the smaller the angle .beta.. Consequently, the configuration of FIG. 2 leads to an increase in the area necessary for integration of the integrated circuit.
In particular, this constitutes a limitation in the case where, on the same wafer, high voltage devices and low voltage devices (for example, of the CMOS type) are to be integrated. In fact, whereas high voltage devices require insulating structures with degrading walls to prevent early breakdown, as has been explained above, low voltage devices do not present this problem, while the increase in overall dimensions due to the presence of the transition regions becomes disadvantageous.
Various processes for forming insulating structures of the type described are known.
According to a first solution, starting from a semiconductor material wafer an oxide layer having the desired thickness is deposited. Then a mask is formed, which covers the entire wafer, except for the regions where the degrading walls are to be formed. A damaging implantation is next carried out, where the species implanted is, for example, arsenic. As indicated in J. Gotzlich, H. Ryssel, Journal of the Electrochemical Society, Vol. 12, No. 3, March 1981, and in J. C. North, T. E. McGahan. D. W. Rice, A. C. Adams, IEEE Transactions on Electron Devices, Vol. ED, No. 7, July 1978, the implantation alters the structural characteristics of the oxide. After removal of the mask, wet etching is carried out, during which, on account of the damage, removal of the oxide itself in the horizontal direction rather than in the vertical direction is favored. As a result, the profile that is obtained at the end of the etching step degrades progressively, forming with the underlying layers angles of between approximately 30.degree. and 60.degree..
With this approach, however, high levels of bulk are obtained, as mentioned above.
A second solution uses the local oxidation (LOCOS) technique. According to this solution, a thin sacrificial oxide layer protecting the substrate is initially formed, and then a silicon nitride layer is deposited. Next, a resist mask is formed, which covers the device active areas and presents windows on the areas where the insulating structures are to be formed. Then, anisotropic etching of the nitride is performed at the windows. After removing the resist mask, a field oxidation is carried out, thus growing field oxide regions in the areas of the substrate that are not covered by the nitride. Finally, the remaining silicon nitride layer is removed.
With the local oxidation technique, the field oxide regions grow in part over the original surface of the substrate and in part beneath, giving rise to intrusions (the so called "bird's beak") having an inclined profile underneath the nitride layer. In this way, clear transitions between the thin oxide layer and the field oxide are avoided; at the same time, the length of the transition regions is reduced.
However, this process presents the drawbacks of being complex and of requiring a high number of fabrication steps. In addition, the oxidation step subjects the wafer to thermal and mechanical fatigue and calls for a preventive implant (for example, of the P-type) to prevent formation of depletion regions underneath the field oxide regions. In fact, the surface of the wafer underneath the insulating structures is impoverished by the field oxidation as an effect of the segregation of doping atoms (for example, boron) by the oxide layer.
A third solution uses the shallow-trench insulating (STI) technique consisting in forming trenches in the substrate and in filling them with silicon oxide. In detail, the regions of the substrate where the insulating structures are to be formed are initially defined through a resist mask laid on the substrate and covering the entire surface thereof, except for these regions. Next, the substrate is etched, for example by reactive ion etching (RIE) until a depth equal to the desired thickness is reached, so forming trenches. Then the mask is removed, and a field oxide layer is deposited over the entire wafer so as to fill the previously dug trenches. Finally, the oxide layer protruding from the trenches is removed through a chemical-mechanical polishing action, the so called chemical-mechanical polishing (CMP) technique.
The described method enables very compact devices to be formed, and hence favors a high integration level; however, it presents the drawback that the walls of the insulating structures have an accentuated slope, with high transition angles. Consequently, the STI technique is very suitable for large scale integration of low voltage devices, whereas it is not suitable for forming high voltage devices